[NET] ESP32 Ethernet: PHY cold-cycle at boot, default on Theengs Bridge (#2364)
Power ETH_PHY_POWER down for 200 ms and back up 200 ms before ETH.begin() so the PHY always gets a true cold start. A warm PHY left in a stale state (reproduced on Theengs Bridge v1.1 with PSRAM enabled after an NVS erase) can flap the link until a manual power cycle: it reports up for one poll, then down for several seconds, forever, so DHCP never completes. The short reset the Ethernet driver performs on its own does not clear that state; a power cycle with a settle window before begin() does. On a hardware-in-the- loop bench the same provocation went from flapping every trial to flapping in none of them (4/4). Enabled via -DETH_PHY_COLD_CYCLE, only active when ETH_PHY_POWER is a valid pin, at the cost of ~400 ms added boot time. Set by default on both Theengs Bridge environments. Co-authored-by: Florian <1technophile@users.noreply.github.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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@@ -74,6 +74,7 @@ build_flags =
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'-DETH_PHY_MDC=23'
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'-DETH_PHY_MDIO=18'
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'-DETH_CLK_MODE=ETH_CLOCK_GPIO0_OUT'
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'-DETH_PHY_COLD_CYCLE'
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'-DLED_ADDRESSABLE_PIN1=32'
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'-DLED_ADDRESSABLE_NUM=4'
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'-DLED_BROKER=0'
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@@ -113,6 +114,7 @@ build_flags =
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'-DETH_PHY_MDC=23'
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'-DETH_PHY_MDIO=18'
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'-DETH_CLK_MODE=ETH_CLOCK_GPIO0_OUT'
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'-DETH_PHY_COLD_CYCLE'
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'-DLED_ADDRESSABLE=true'
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'-DLED_ADDRESSABLE_PIN1=32'
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'-DLED_ADDRESSABLE_NUM=4'
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@@ -2475,6 +2475,19 @@ void setupWiFiManager() {
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void setup_ethernet_esp32() {
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bool ethBeginSuccess = false;
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WiFi.onEvent(WiFiEvent);
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# if defined(ETH_PHY_COLD_CYCLE) && defined(ETH_PHY_POWER) && (ETH_PHY_POWER >= 0)
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// Give the PHY a true cold start before begin(): a warm PHY left in a stale
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// state (seen after an NVS erase with PSRAM enabled on Theengs Bridge v1.1)
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// can flap the link until a manual power cycle, and the in-driver reset
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// begin() performs (short assert, short delay) does not clear it. Power the
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// PHY down, then back up, and let its oscillator settle before begin()
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// starts talking to it.
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pinMode(ETH_PHY_POWER, OUTPUT);
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digitalWrite(ETH_PHY_POWER, LOW);
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delay(200); // hold the PHY powered down
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digitalWrite(ETH_PHY_POWER, HIGH);
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delay(200); // let the PHY oscillator settle
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# endif
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# ifdef NetworkAdvancedSetup
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THEENGS_LOG_TRACE(F("Adv eth cfg" CR));
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// ETH.config() has to be called after ETH.begin(): the underlying netif is
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